During Integrated Chip (IC) fabrication, the semiconductor wafer on which the chips are fabricated are processed through a multitude of fabrication steps like oxidations, thin film depositions, doping implants, photolithography and plasma etching. Some of these steps like plasma etching and film deposition processes, can cause electrical charge to accumulate on interconnect metal interconnect segments that are coupled to the transistor. The accumulated charge can cause damage to the transistor by discharging through the transistor to the substrate (i.e. ground). For example, accumulated charge on interconnect metal segments that are coupled to a gate of a transistor can discharge through the gate and, thereby, damage the transistor's thin gate oxide. The short-term and long-term characteristics and reliability of the transistors are affected by such discharge events.
With the scaling of technology, it has becoming increasingly important to study, characterize and isolate the causes of charging damage in the fabrication process. The gate dielectrics are becoming increasingly thinner, and the number of interconnect levels are increasing with each technology generation. To determine how much charge damage has occurred to a transistor as a result of wafer processing, characterization structures are designed and placed in the scribe lines. The characterization test structures are designed to have different lengths of interconnects connected to the gates of transistors to mimic what happens on the actual IC. These long interconnects usually connected to the gate are usually referred to as antennas. There is usually a matrix of test structures with connection to interconnect antennas at different metal levels. The characterization can be performed on real production wafers or on test wafers which only get processed through a part of the actual fabrication process. After a desired number of interconnect metal layers have been fabricated, the wafer designated for characterization can be tested for charge damage. The characterization usually involves measurement of transistor characteristics like drive current, threshold voltage, gate leakage current, sub-threshold slopes, transconductance, etc. The damage is assessed by comparison to a reference transistor with no antenna attached to it.
Since the charge collected accumulates through processing of the interconnect levels, it is desired to measure the cumulative damage to the transistor though the full processing flow. It is also desirable to understand and isolate which particular step or series of steps is responsible for the most damage. So, in addition to the measurement of cumulative damage where antennas are connected to the gate at all interconnect levels, it is a known art in the industry to connect antennas to a given metal level (e.g. M1) and to have an antenna-protection device like a diode connected at the level one above (M2 here) so that the diode can shunt all the charge from processing interconnect levels above the level of interest (M1 here).
However, the presence of the diode in parallel with the transistor gate interferes with certain characterization measurements where the diode gets forward-biased and conducts currents to the substrate preventing the transistor from being properly biased for the measurement.
Also, it is desirable to be able to characterize all the interconnect metal level charging on a single wafer which has been processed through the whole flow to avoid wafer-to-wafer and lot-to-lot variations present in the fabrication process. So in order that valuable wafer processing time is not consumed in measurement and characterization at each interconnect level, it is desirable that the measurements be done at the end of the process flow. In addition, it is not uncommon in fabrication facilities that the wafer has to be removed from the cleanroom environment for measurement, in which case it is undesirable to put the wafer back into the fabrication cleanroom once the measurement is done for fear of contamination during testing and measurement.